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Multicore SoCs invade embedded arena

Posted: 20 Apr 2010 ?? ?Print Version ?Bookmark and Share

Keywords:multicore SoC? processor? OS? embedded market?

Divide the system into two OS domains (let's say an RTOS and some type of GPOS), where each domain is in charge of two cores. Cores 0 and 1 belong to OS domain 0, and cores 2 and 3 belong to OS domain 1. As long as all operating system instances support both SMP and AMP operation, the most ideal configuration can be realized.

Application designers or system integrators usually run into trouble when they migrate code developed for a single core across several cores in an SMP system. This introduces two important issues: Is your code multicore ready, and can your code take advantage of multiple cores?

Multicore-ready code
When preparing to run your code on an SMP scheduler, it's important to consider all priority dependencies that can break your code. There are two main causes of potential problems when running code in a multicore system:

1. Using the master interrupt as a global semaphore. A semaphore is an object used to prevent simultaneous access to a shared resource. However, it is common on single core OS to use the master interrupt as a "fast" system-wide semaphore. It looks like this:

Disable Interrupts
Access and update the global data structure
Enable Interrupts

You can see from the above pseudo-code that not even an interrupt can execute while the global data structure is being accessed, which works great on single core systems and can be much faster than using a semaphore object for protection.

But therein lies the problem. When there are two cores in operation, and the code is executed, interrupts are disabled only on the core in which it is currently operating , thereby leaving the data structure open for access on other SMP scheduled cores. This race condition will leave the system open to unpredictable results.

Hybrid AMP/SMP on SMP architecture

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