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Stratix FPGAs deliver up to 1.6Tbit/s serial switching

Posted: 21 Apr 2010 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? DSP? ASIC? Ethernet?

Stratix V FPGA

Altera Corp. has disclosed more details about its 28nm high-end Stratix V FPGA family, saying the devices will offer up to 1.6Tbit/s of serial switching capability, 1.1 million logic elements and 53Mbit embedded memory. The FPGAs would also offer up to 3,680 18 x 18 multipliers and integrated transceivers operating up to 28Gbit/s.

The company would use the high-performance manufacturing process from foundry Taiwan Semiconductor Manufacturing Co. (TMSC), a clear divergence from larger rival Xilinx Inc. In February, Xilinx said it would switch to TSMC for manufacturing at the 28nm node. But Xilinx, which is placing special emphasis on low power consumption at the 28nm node, chose TSMC's high performance/low-power manufacturing process.

According to Luanne Schirrmeister, senior director of product marketing at Altera, while customers are always demanding reductions in power, they are also telling Altera that they need the performance to support next-generation communications infrastructure deployments. "Nobody is telling us that it's okay to run a slower core," she said.

Schirrmeister added that the key is always to strike a balance between performance and power consumption. But, she said, "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."

According to Bruce Fienberg, a Xilinx spokesperson, Xilinx chose TMSC's high-performance/low power process because the company is focused on lowering power consumption without sacrificing performance at 28nm. Xilinx's strategy is to reduce static power consumption, which at this process node makes up a significant portion of total power, Fienberg said. Without the focus on power, customers will be unable to take full advantage of the higher performance offered by the 28nm technology and stay within their power budgets, according to Fienberg.

"The path we've chosen doesn't sacrifice performance," Fienberg said. "But you need do really get the static power down so you can offer high performance that the customer can actually use."

According to Altera, TSMC's high-performance process, which uses high-k metal gate technology, offers roughly 35 percent higher performance than alternative process options and 30 percent lower total power compared with previous generations.

Xilinx's February announcement said that compared to the standard high-performance process, the high-performance/ low-power process delivers FPGAs that are 50 percent lower in static power. This lower static power contributes to a 50 percent reduction in total power compared to previous generation devices, according to Xilinx. The company's development tools will also reduce dynamic power as much as 20 percent through innovative clock management, according to Xilinx.

In February, Altera disclosed several innovations it plans to introduce at 28nm, including partial reconfiguration, 28Gbit/s transceivers and embedded hard intellectual property (IP) blocks.


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