Programmable Yn clock phase shift with SN74SSQEA32882 DDR3 register

This application report describes how to shift the Yn clock position on TI's DDR3 register SN74SSQEA32882 (V4.2) by using extended CMR commands. This Yn clock position shift can be used for the analysis of post register margin at the DRAMs. Note that this application report does not apply to SN74SSQE32882 (V3.1).

SSTE32882-compliant DDR3 registers have internal control bits (also called Control Mode registers) to configure certain device features.

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