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Understanding high-level synthesis design's advantages

Posted: 26 Apr 2010 ?? ?Print Version ?Bookmark and Share

Keywords:high level synthesis? design synthesis? design verification?

High-level design has many advantages over the more commonplace design flow, which begins with RTL code. Among the most compelling advantages is the improved verification efficiency, which a higher level of abstraction offers. It is apparent to the point of being self-evident that when the source code of a design is created, there will be fewer errors if the source is at a higher abstraction level than if it is at a lower level. However, there is still a process required to verify the transformations, which are applied to the design description as it proceeds through the design flow from creation to final realization.

Verification should take place as close to the original source code as possible. In the context of ESL design, that means that simulation should be done before high-level synthesis, not after. However, language limitations force verification of inter-module communication to be done at one level or the other. With SystemC, verification can take place before high-level synthesis. With Ansi-C/C++, verification must be done after synthesis. This is a serious limitation.

We can summarize with the dictum "Synthesize what you simulate." Simulation is the verification step. It is vitally important to verify the design before performing high-level synthesis, not after. It is not effective to synthesize a design that does not work.

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