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FPGA design suite includes intelligent clock gating

Posted: 06 May 2010 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? clock gating? power consumption? interconnect?

Xilinx Inc. has launched a new version of its ISE Design Suite to support its Virtex-6 and Spartan-6 FPGA families. The ISE 12 adds intelligent clock gating technology, advances in timing-driven design preservation, AMBA 4 AXI4-compliant IP support and easier-to-use partial reconfiguration capabilities.

The intelligent clock-gating technology reduces dynamic power consumption by as much as 30 percent. The technology automatically detects and neutralizes unnecessary transitions with fine grain optimizations, Xilinx said, using algorithms that analyze designs, indentifying elements that do not change downstream logic and interconnect when toggled.

The intelligent clock gating technology is most apt for encryption and other computationally intensive designs, according to Hitesh Patel, director of ISE foundation product marketing at Xilinx. The clock gating algorithms will in some cases add a small amount of logic to designs, Patel said.

Patel said ISE 12 also features a productized design flow for Xilinx' partial reconfiguration technology that will make the technology user to use. Xilinx has offered partial reconfiguration for years, but Patel acknowledged that it has to date been cumbersome to implement and not widely used outside of specific applications. The new partial reconfiguration flow in ISE 12 is easier to use and intuitive, he said, using familiar Xilinx tools and techniques for timing closure, design management and floorplanning and design preservation.

"Users do need to understand that there is a methodology they need to follow [to implement partial reconfiguration]," Patel said. "But if they do follow the methodology, it's much easier to use."

Asked if the ease of use improvements will prompt more users to implement partial reconfiguration, Patel said, "I think it's at a point where a lot more people will say, 'let me try this on my design.' "

ISE 12 also adds advanced design preservation capabilities to enable designers to reach design closure fast with repeatable timing results, according to Xilinx. The tool lets designers partition designs to focus on achieving timing for critical blocks, then lock those blocks to preserve placement and routing while they work on the rest of the design, Xilinx said.

Xilinx also said it is standardizing IP interfaces on the open AMBA 4 AXI4 interconnect protocol in order to foster plug and play design. The company said it worked with ARM Holdings plc to define the AXI4, AXI4-Lite and AXI4-Stream specifications for efficient mapping into its FPGA architectures.

Standardizing on AMBA 4 AXI4 will make it easier for customers to connect different IP blocks provided by Xilinx and third party vendors, Patel said.

Xilinx is rolling out ISE 12 in phases, with intelligent clock gating for Virtex-6 designs shipping now with the 12.1 release, the company said. The partial reconfiguration enhancements will be available in the 12.2 release, set for summer, Xilinx said, while AXI4 IP support will follow with the 12.3 release in the fall.

The 12.1 software features an average of 2x faster logic synthesis and 1.3x faster implementation run times for large designs than previous versions and an improved embedded design methodology.

The list price for ISE 12.1 starts at $2,995 for the Logic Edition. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx Website. More information about the tools is available on Xilinx' Website.

- Dylan McGrath
EE Times

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