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Synthesis tool handles complex design verification

Posted: 11 May 2010 ?? ?Print Version ?Bookmark and Share

Keywords:SoC design? verification? synthesis tool? EDA?

EDA startup NextOp Software Inc. is bridging design and verification with the introduction of what it claims is the first assertion-based verification solution to automatically generate high quality assertions and functional coverage properties from testbench and RTL.

The company's initial product, dubbed BugScope, is a full-chip assertion synthesis product that leverages design and testbench information to automatically generate assertions and functional coverage properties for progressive and targeted verification of complex designs, said Yunshan Zhu, CEO of NextOp, in an interview with EDA DesignLine at Embedded Systems Conference.

SoC design complexity is continuously growing, and engineers cannot possibly imagine all of the corner-case behaviors let alone write tests to exercise them. Without an adequate specification, the debugging cycle will continue to increase, and specification results from a communication mechanism between the design and the verification team, outlined Zhu.

He suggested that the only way to address the growing complexity is to supplement traditional functional verification methods by combining assertions, simulation, and formal techniques in a process called assertion-based verification.

However, Zhu said it is infeasible to manually generate an adequate number of assertions for thorough identification of design problems. One assertion is required for every 10 to 100 lines of RTL code, and it takes hours to create, debug and maintain each assertion.

There intervenes assertion synthesis to enable the proliferation of assertion-based verification by automating the tedious and time-consuming process of generating assertions and coverage properties. There intervenes NextOp's software, BugScope, to "finally reap the benefits of assertion-based verification in a timely and resource efficient manner," the company claimed.

Zhu commented: "Assertion is a way to leverage your effort across the whole verification platform. It is a way to specify the RTL. However, this is an area that has very little automation today."

To fill the gap, Zhu explained, BugScope automatically synthesizes high-quality assertions to capture key design constraints and specifications. The assertions provide orthogonal perspective from the RTL implementation.

It also automatically synthesizes functional coverage properties which expose holes in the testbench. The coverage properties are independent of RTL syntax and coding style.

Another point of interest, according to Zhu, is the fact that BugScope enables progressive, targeted functional verification. Indeed, as development teams progress through their design and verification iterations, the number of coverage properties produced by BugScope will decrease relative to the number of assertions, until such point that there are only assertions with minor coverage properties.

Throughout the iterations, the assertions are bound to the corresponding RTL, ensuring that any modification to the RTL does not introduce new bugs. And, when an assertion is triggered, it pinpoints the location of a bug, thus reducing the debug turnaround time, the company stated.

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