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Comms processors pack up to 32 cores

Posted: 13 May 2010 ?? ?Print Version ?Bookmark and Share

Keywords:communications processor? multicore? base station? LTE?

Cavium Networks is expanding its Octeon II family with two new members that upgrade and double the number of cores available on the communications processors to 32. The new products highlight the growing trend to use of multicore architectures to handle increasing processing needs in broadband networks.

The rise of smart phones, netbooks and other mobile devices is driving upgrades in network infrastructure such as Long Term Evolution base stations that will use Octeon II chips. "The dramatic increase in mobile data is a really good trend for us," said Syed Ali, CEO of Cavium.

The company has chips in at least two LTE base stations now in early stages of design. The systems may have "some small deployment at the end of year, but wide deployment is more like 2012," said Ali.

The new systems represent an architectural shift, Ali said. Past base station designs used arrays of DSPs to handle media access control (MAC) and PHY processing, small specialty processors to handle packets and control plane processors to oversee the whole system.

"For the next generation, OEMs are essentially collapsing these functions into two chipsa DSP does all the PHY and some of the MAC jobs and a multicore processor takes on some of the MAC and the data and control plane processing, so the number of components is collapsing dramatically," Ali said.

The new Octeon II 6800 and 6700 processors use cnMIPS version 2.0 cores running at up to 1.5GHz with up to 4Mbyte L2 cache and support for DDR3 memory. They can run at about 600MHz/W, triple the rate of Cavium's prior generation.

They use the same abstraction logic as Cavium's past two- to 16-core processors. Thus they use existing Cavium programming methods.

Cavium's largest competitors including Freescale and NetLogic typically use one- to eight-core processors. NetLogic lets users link up to four processors, adding memory bandwidth with each chip.

"One reason Freescale stops at eight cores is they want to cap power dissipation at about 30W compared to 60W or more for Cavium's biggest chips, said Joe Byrne, senior analyst at market watcher the Linley Group.

In addition, "the fastest chips are also ones with leakiest transistors, so power could scale faster than the clock rate," Byrne said. "It's going to be a hot chip but you get a lot of resources for it," he added.

Emerging companies including Tilera and PicoChip leapfrog Cavium's chip with 100 or more processors and their own approaches to parallel programming, also targeting communications systems.

- Rick Merritt
EE Times

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