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ESD physical integrity tool enables early prototyping

Posted: 14 May 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ESD? integrity tool? prototyping?

From Apache Design Solutions Inc. comes what it claims is the first ESD integrity solution targeted to address the increasing reliability challenges faced by nanometer designs.

Apache said PathFinder, based on proprietary modeling, extraction and simulation technologies, aims to enable designers to perform early prototyping, circuit optimization and full-chip signoff. It helps designers identify the most vulnerable area of the design, meet ESD guidelines and improve product yield.

Apache acknowledged that electronic components have faced ESD failures for many years but, more recently, the impact of ESD has gotten worse. The main causes of ESD failure, the company specified, are the shrinking geometries, the higher levels of digital and analog integration with isolated and independent power and ground networks. The company also mentioned the broader use of handheld devices resulting in more direct access to IC components and, finally, the advanced packaging designs with tighter pitch and complex shapes.

Outlining PathFinder's productivity benefits, Apache cited the 100 million instances with overnight turnaround time for static ESD verification, the coverage with full-chip analysis of ESD events such as human body model, machine model and charged device model. Apache also highlighted the SPICE-like accuracy for dynamic ESD simulation of 100s of thousands of transistors block, including clamping devices and their snap-back characteristics, as well as layout-based GUI environment for cross probing, 'what if' analysis and device failure rankings.

Using full-chip level static techniques, Apache said PathFinder can verify that the design meets ESD guidelines, and identify weak areas of the design in layout or circuit. It can report if the current density exceeds the limits for wires, vias and clamps and provide a GUI environment for debugging the violating paths. Moreover, PathFinder can perform early prototyping and design exploration, helping designers make area and metal routing tradeoffs, the company added.

Currently, there is no competing ESD solution at the full-chip level for ESD electrical analysis and sign-off, indicated Dian Yang, general manager and senior vice president of Product Management, to EDA DesignLine.

Historically, there are some ESD rule checking solutions based on geometry patterns and netlist structures," Yang specified. "But our solution is electrical analysis and simulation based."

Asked if Apache had identified new noise and power integrity challenges as the process technologies move towards 22nm, Yang declared: "As the technology process advances, designers are facing more power and noise integrity challenges. In addition to the ESD, we also see on-die inductance coupling, substrate noise for mixed signal designs as well as EMI."

STMicroelectronics NV said it has been partnering with Apache for the past two years and has evaluated PathFinder. Philippe Magarshack, group vice president, Technology R&D at STMicroelectronics, commented: "The ability to analyze ESD design robustness at the full-chip and macro levels is key to managing our overall system cost. Apache's PathFinder enables us to perform ESD analysis and signoff in a reasonable amount of time."

Yang said PathFinder has been adopted by over ten customers in the last two years.

- Anne-Francoise Pele
EDA DesignLine





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