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60GHz chipset steers 5bit/s around obstacles

Posted: 27 May 2010 ?? ?Print Version ?Bookmark and Share

Keywords:60GHz transceiver? receiver? transmitter?

IBM and MediaTek Inc. have unveiled their 60GHz transceiver chipset at the IEEE Radio Frequency Integrated Circuit Symposium.

The partners have been cooperatively developing the chipset for IEEE's Wide Personal Area Network standard, which will replace that snarl of cables connecting video, audio and control signals among multimedia equipment. The transmitter chip had been previously described by IBM and MediaTek, but this is the first time they have described the receiver chip. The matched chipset is expected to be commercially available by next year.

Because 60GHz signals cannot penetrate solid objects, they are confined to individual rooms. They also can be interrupted by people or other objects in a room. To compensate, IBM and MediaTek have downsized military phased-array radar technologies to a single chip, allowing 60GHz transmitters to steer the beam around obstacles between it and the in-room receivers to which signals are being routed.

"We have a low-cost, manufacturable, multi-layer, organic package with 16 wide-bandwidth phase array antennas inside to cover all four of the IEEE 60GHz channels," said Scott Reynolds, a researcher at IBM's T. J. Watson Research Center in Yorktown Heights, N.Y. Reynolds worked closely to develop the chipset with MediaTek.

The IBM/MediaTek 60GHz receiver chip has a die size of 6.08mm by 6.2mm.

"Millimeter wave frequencies are really line of sight," Reynolds said. "So when something blocks it, instead of the signal being interrupted, we can steer the beam around obstructionsbouncing the signal off the wall or the ceiling as necessary."

IBM and MediaTek's chip will work with algorithms that catalog alternative routes for every signal passing through it, so that when obstacles suddenly appear in a room, the chips will already have an alternative route to which it can quickly switch. The partners have demonstrated continuous 5Gbit/s speeds even when the line-of-sight is blocked and the chipset must switch routes.

The silicon-germanium (SiGe BiCMOS8HP) process houses all circuitry, including 16 planar antennas, in an industry-standard 288-pin BGA package using a 120nm design rules. The 16 phase-shifting RF front-ends use 11 digital phase resolution along with hybrid passive-active signal combining techniques to achieve a 7.4 to 7.9 noise figure over all four IEEE channels.

A double-conversion superheterodyne receiver core has a silicon area of 38mm?, 72dB of gain and draws about 1.8W at 2.7V.

- R. Colin Johnson
EE Times

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