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Cadence, IBM co-develop 32nm SOI IP

Posted: 31 May 2010 ?? ?Print Version ?Bookmark and Share

Keywords:IP? 32nm SOI? EDA?

Cadence Design Systems Inc. and IBM have entered a joint development agreement to create high-performance integration-optimized IP that will help customers deliver leading-edge designs while reducing the risk and time associated with integrating complex SoC Designs.

Under the agreement, the companies will develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32nm silicon-on-insulator (SOI). The technology will be used in servers, video games and other devices and will be available through the newly announced Cadence Open Integration Platform.

A core component of its EDA360 vision, the Cadence Open Integration Platform comprises an integration design environment, integration-optimized IP and on-demand integration services, all facilitated by Cadence's leading mixed-signal and digital design, verification and implementation technologies.

"Qualifying and integrating complex IP is a costly and growing burden for many of our customers," said Vishal Kapoor, VP, product management of Cadence. "We look forward to teaming with IBM to relieve some of that burden for engineering teams as they grapple with SoCs and systems that will only continue to grow in size and complexity."

"The IP we're working on with Cadence will provide state of the art building blocks that will allow our customers to build more powerful, higher bandwidth networking and communications technology," said Marie Angelopoulos, director, IBM Microelectronics. "This collaboration with Cadence combines IBM's expertise in developing and integrating process and IP technology with Cadence's experience in IP development to supply customers with the tools needed to build a new generation of communications infrastructure."

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