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Scaling custom digital layout for next-generation chip design

Posted: 07 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:chip design? custom digital layout? 40nm semiconductor?

Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs. But designs that require the utmost in performance and/or the smallest possible area are still done "by hand" using custom IC layout methodologies.

In the next generation of custom chips, complicated rules, tight time-to-market schedules, and the sheer size and complexity of designs are making full-custom digital blocks increasingly difficult to implement. Fully-automated APR flows cannot offer the kind of interactive control of the layout and routing that is necessary. Designers need a highly-automated yet controllable full custom digital IC design flow that optimizes performance, speed and area.

This article details how one digital IC design team at a large fabless semiconductor company in the consumer product market is leveraging standards-based tool interoperability to maintain the benefits of hand layout for large, performance-sensitive 40nm designs. The team has deployed the integration capabilities made possible by the Silicon Integration Initiative's (Si2) Open Access (OA) interoperability standardization effort with tools from multiple vendors to form a more productive custom IC layout flow.

View the PDF document for more information.

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