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EDA/IP??

Tools offer shared database for design, verification

Posted: 08 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:chip design? formal verification? RTL?

From Jasper Design Automation Inc. come improved versions of the ActiveDesign and JasperGold tools with capabilities that bridge the divide between chip design and verification by sharing a common, persistent knowledge base.

Jasper's ActiveDesign with behavioral indexing lets users design, concurrently modify and verify their RTL code, then store it in a persistent database containing both the RTL itself and an "index" of its elastic behaviors. This information is shared downstream with the JasperGold verification team, facilitating increased collaboration between groups. Benefits are unity among multiple design groups and verification teams, a reduction in information demand on designers, acceleration of verification, and increased IP reuse since design behaviors are now archived and easily accessible.

"ActiveDesign and JasperGold work synergistically. Designers using ActiveDesign explore blocks, waveforms and their key behaviors, creating and archiving important information," said Rajeev Ranjan, Jasper chief technology officer. "ActiveDesign can then export properties (asserts, assumes, covers, in SVA and PSL) for transfer to other designers or verification teams using JasperGold."

In addition, Jasper has added several new capabilities to its tools. The ver.2.0 of ActiveDesign adds several new, automated fast-start and collaboration features. EasyStart automates the identification of clocks and resets. AutoExplore examines behaviors of interest by displaying contributing causes and paths back through the design to show causality. With concurrent modification, several designers can work on the same code while an intelligent management system prevents overwriting. ActiveDesign's hierarchical design support lets an RTL block to be instantiated repeatedly at different levels in the design to efficiently deal with complexity, and a parallelization feature distributes ActiveDesign across multiple platforms for increased throughput.

The ver.7.0 of JasperGold/JasperCore also has new features. JasperGold Formal Verification System has a new engine technology and modeling abstractions, which the company claims delivers 50 per cent higher performance and capacity. ProofGrid and ProofGrid Manager support user-controlled and distributed proof engines to reduce the time needed to reach full proofs. A new management capability accelerates convergence of deep formal proofs, leveraging Jasper's design-space tunneling and promoting both proactive and after-the-fact RTL tree exploration of design complexity. JasperGold now has enhanced handling of such formal verification tasks as X-propagation, multi-cycle path analysis, clock domain crossing, and certification of the latest protocols such as DFI and AMBA 4 (enabled by Jasper Proof Kits).





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