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ST readies 20nm tape out in 2012

Posted: 09 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ST 22nm? foundry? CMOS? wafer fab?

STMicroelectronics NV chief technology officer Jean-Marc Chery announced the company will be ready to tape out designs using a 20nm CMOS low-power (LP) process technology in Q4 2012.

However, ST is not indicating it will ready to make those designs itself, which raises questions about how long ST can rely on its 300mm wafer fab in Crolles, near Grenoble, France to be its leading-edge R&D and production site.

At the company's annual analysts' day, executives said ST was aiming at 5 to 7 percent capex to sales ratio as part of the "asset lighter" strategy the company is pursuing. It achieved 5.3 percent in 2009. However, that appears to leave no room for ST to ever lay down the several billions of dollars needed to wholly-own a new leading-edge fab.

Whatever does get taped out in a 20nm design in 2012 is likely to be manufactured first at GlobalFoundries' wafer fab in Dresden, Germany or another foundry that is also in the International Semiconductor Development Alliance (ISDA) based around IBM Microelectronics. It could even be one of the first designs to be made at a newly-opened GlobalFoundries fab in New York.

GlobalFoundries is known to be working on a 22nm process at Dresden which will be used to start operations at the Albany fab that is under construction.

"I am very confident we will be able to tape out 20nm LP in Q4 2012," said Chery. His slide showed that while work on 20nm is for delivery to ST through an ISDA fab is beginning now in the second quarter of 2010, the same work for delivery through an ST fab is not due to start until Q1 2012.

ST has some processes on its roadmap including general purpose 40- and 28nm that it does not intend to be able to manufacture itself, according to Chery's presentation.

"Beyond 20nm we will have to change the transistor architecture. Planar will be unable to sustain [suitable operation] below 20nm." Chery said ST faces a choice between fully-depleted silicon-on-insulator (FD-SOI) and FinFETs. Of course ST will only be a participant in those decisions, which are likely to be taken among the lead manufacturing partners within ISDA.

"Unfortunately you must use double-patterning, which effects productivity." Chery said he expects cost of ownership issues around extreme ultraviolet lithography to be "confirmed" in the third or fourth quarter of this year allowing decisions about a move to extreme ultraviolet lithography to be taken thereafter.

- Peter Clarke
EE Times





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