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Virtex-6, Spartan-6 ref design gets PCI-SIG-certified

Posted: 17 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA reference design? PCIe? transceiver?

Xilinx Inc.'s Spartan-6 and Virtex-6 FPGA connectivity targeted reference design passed the PCI-SIG compliance and interoperability testing for PCIe 1.1 single-lane configuration with on-chip GTP serial transceivers running at 2.5Gbit/s.

The Virtex-6 FPGA Connectivity Targeted Reference Design passed PCI-SIG compliance and interoperability testing for PCIe 2.0 x4-lane Gen2 configuration with the GTX Serial transceivers running at 5Gbit/s. Both targeted reference designs provide a platform for advanced serial I/O design for use in applications such as wired communications systems, wireless infrastructure, audio, video, broadcast, industrial, automotive infotainment, aerospace, defense and high-end consumer devices. Xilinx first integrated compliant PCIe version 1.1 blocks into programmable devices with its Virtex-5 family and has continued its momentum of PCIe support by achieving PCI-SIG compliance with Virtex-6 and Spartan-6 FPGA devices.

"Xilinx recognized early the importance of providing proven PCIe solutions that allow customers to easily incorporate the capability without spending months of learning and evaluation," said Xilinx director of platform marketing, Brent Przybus.

"The validation through compliance of these Targeted Design Platforms in addition to compliance of blocks and transceiver technology with PCIe standards reinforce our commitment to the underlying technology and making it easily accessible to customers."

- Colin Holland
Programmable Logic DesignLine





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