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Silicon-validated library tailored for 28nm designs

Posted: 22 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:silicon solution? 28nm design? design flow? silicon library?

GlobalFoundries rolls a silicon-validated solution to help customers accelerate time-to-volume for complex SoC designs at 28nm and beyond. Called DRC+, the technique goes beyond standard design rule checking (DRC) and uses 2D shape-based pattern-matching to enable a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.

"As the industry continues to adopt more advanced process technology, it becomes increasingly critical for foundries to provide customers with the tools to ensure first-silicon success," said Mojy Chian, senior VP of design enablement at GlobalFoundries. "Standard DRC is challenged to capture design issues that could impact the manufacturability of an integrated circuit. With DRC+, we are improving upon the traditional approach and giving customers increased visibility into potential manufacturability issues, earlier in the design flow."

Until now, a designer has only had two primary options for identifying design-for-manufacturing issues during the SoC design cycle: run accurate but computationally intensive simulations based on numerical algorithms, or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success. For example, some have proposed the use of restrictive design rules that only allow highly regular structures for layout, avoiding problematic 2D geometries altogether. The potential drawback is that designers cannot effectively optimize their circuits to meet application requirements with overly constrained design rules.

DRC+ takes a different approach. Instead of restricting the flexibility of designers, the technique augments standard DRC by applying rapid 2D shape-based pattern matching to identify problematic configurations that could be difficult to manufacture. The tool then returns specific feedback to designers on how to resolve these issues.

As a critical component of DRC+, GlobalFoundries is now offering customers what it claims to be the first silicon-validated libraries of yield-critical patterns for technologies at 28nm and below. In tests run at GlobalFoundries, DRC+ identified known problem patterns at speeds comparable to traditional DRC verification engines-leading to a 100-fold improvement in the speed of hotspot detection, without sacrificing accuracy.

DRC+ augments and completes the overall DFM solution provided by GlobalFoundries, together with rule-based DFM verification and model-based litho/etch and CMP simulators, which can identify new yield-detracting patterns, as process conditions and design styles change over time, during technology development. As the process matures, DRC+ pattern-matching-based verification at the full-chip level can then be used to achieve increasing performance improvements, at the highest level of accuracy. By improving verification speed, DRC+ can have a direct impact on the ability to rapidly ramp a product to volume and accelerate time-to-market for customers.

The innovative DRC+ verification flow has been successfully used on several 32nm production IC designs and libraries of yield-detractors patterns for 28nm technology nodes are currently available from GlobalFoundries for foundry customers.

"A DRC+ solution based upon the Calibre platform, which is used both in manufacturing and the design flow at GlobalFoundries, allows mutual customers to fully leverage new process capabilities," said Joe Sawicki, VP and general manager of Mentor Graphics' design to silicon division. "Leveraging the unique breadth of Calibre integrations with all major design environments, designers can mix model-based and pattern-based verification as to achieve the shortest possible tape out cycle time."

"Cadence and GlobalFoundries have been longtime collaborators working together on DRC+, including validation through silicon tapeouts," said Wilbur Luo, group director of DFM enablement at Cadence Design Systems. "The combination of high performance and accuracy allows for the detection and prevention of printability issues early in the design flow, helping ensure more efficient silicon realization. We have enabled DRC+ in our SoC and mixed-signal in-design DFM flows, and in our sign-off verification solutions, to address the time-to-volume requirements of our mutual customers."

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