Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

LatticeECP3 and LatticeECP2M high-speed backplane measurements

Posted: 22 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:backplane measurements? serdes backplane transmission? LatticeECP2M measurements?

The LatticeECP3 and LatticeECP2M families are low-cost FPGA product lines offering high-end features such as high-speed, embedded serdes interfaces. These devices feature up to 16 serdes channels with data rates of up to 3.125Gbit/s.

This technical note outlines two experiments that measure the serdes backplane transmission performance thresholds of the LatticeECP3 and LatticeECP2M devices.

View the PDF document for more information.

Click here to view related datasheets.





Article Comments - LatticeECP3 and LatticeECP2M high-sp...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top