Elpida, PTI, UMC team on 3D IC integration for 28nm

Elpida Memory Inc., Powertech Technology Inc. (PTI), and United Microelectronics Corp. have reached a three-way cooperation to advance 3D IC integration technologies for advanced processes including 28nm. This collaboration will leverage the strengths of Elpida's DRAM, PTI's assembly and UMC's foundry logic technologies to develop a total 3D IC Logic+DRAM integration solution.

"Last year Elpida was the first to successfully develop an 88Gbit DRAM based on TSV (through-silicon-vias) technology," said Takao Adachi, director and chief technology officer of Elpida. "The big advantage of this technology is that it enables a large number of I/O connections between logic and DRAM devices. This can massively increase the data transfer rate and reduce power consumption, making possible completely new kinds of high-performance devices. However, we need a solid partnership with a logic foundry to make this happen. The joint development that we now plan with UMC means that we can use the most advanced TSV integration technology to bring together our advanced DRAM technology and UMC's leading-edge logic foundry technology including experience in providing SoC solutions such as advanced microprocessors. Our plan now is to speed up development in a way that supports ultimate system solutions that will be made possible by freely joining together all kinds of devices through TSV integration."

Adachi added that moving forward with TSV integration would require less expensive product technology and a manufacturing process that can handle large-volume production on neutral ground. "We can accomplish this by working with PTI, which brings advanced assembly technology to our partnership. We believe this 3-way cooperation will allow us to deliver a variety of services using TSV technology and enable customers to build more powerful high-performance systems," Adachi said.

"This 3D IC integration with TSV technology can completely match PTI's business and technology strategy. PTI has been providing advanced memory package and testing services to global 1st tier memory companies by using wafers as thin as 50um and superb die attach technology which enables 8Die to be stacked in one package in commercial base for smart phone applications," noted Iwata, PTI senior VP and R&D chief technology officer. "PTI has also been developing a stacked package with 16Die or more to maintain a low package profile. Meanwhile, PTI has been developing SiP for Logic customers since 2007, which we equip with WLCSP, Flip Chip and Passive components by wire bonding and SMT technologies such as System In Module for mobile handheld devices. PTI commits to this collaboration with Elpida and UMC in order to realize high performance from 3D IC integrated devices that are cost effective and contribute to the evolution of the semiconductor industry."

"With the increasing technology and cost challenges of CMOS scaling, 3D-IC with TSV becomes another viable 'More than Moore' option. However, customers requiring 3D-IC TSV solutions for next generation products are currently encountering multiple challenges such as standardization, supply chain infrastructure, design solutions, thermal stress, integration of package and testing, cost and etc," explained S. C. Chien, VP and head of advanced technology development at UMC. "As a foundry provider of integrated 3D-IC solutions, we are excited to partner with Elpida and PTI to develop a fully integrated TSV solution suitable for a wide range of applications. Leveraging UMC's leading-edge logic technology and logic design interface with Elpida's DRAM/TSV technology and PTI's packaging and testing, this joint development project will allow us to provide our customers with a total solution for their 3D IC designs."

Close integration of DRAM and logic technologies using TSV technology are expected to deliver the performance required for the ongoing convergence of communication, consumer and computing applications with mobile and handheld electronics. The collaboration will facilitate the development of a total solution that includes Logic+DRAM interface design, TSV formation, wafer thinning, testing and chip stacking assembly for customers. The resulting technology is expected to increase cost competitiveness, improve logic yield impact, and accelerate entry into the 3D IC market.