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LatticeSC PURESPEED I/O adaptive input logic user's guide

Posted: 24 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:input logic? logic user guide? Purespeed I/O?

Today's high speed synchronous interfaces pose challenges to the designer in maintaining clock-to-data relationships, managing data-to-data skew and sustaining jitter tolerance. Many next-generation interconnects use Serdes-based interfaces where the clock is embedded inside the data signal. Serdes-based interfaces, however, provide challenges in other areas such as data signal encoding, run length and power.

Lattice has developed an innovative technology to provide data recovery using virtually any input pin on the LatticeSC device. A typical CDR oversamples data by using multiple phases of a reference clock. The novel approach of the LatticeSC AIL oversamples the data using multiple phases of the data. This unique method uses less power and provides receiver performance that in many cases exceeds traditional CDRs.

View the PDF document for more information.

Click here to view related datasheets.





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