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PCIe 3.0 compliance testing pushed back to 2011

Posted: 25 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe? PCIe 3.0 delay? interconnect? Ethernet?

Extending the widely used PCIe interconnect to the next big speed level has proved harder than anticipated.

The PCI Special Interest Group (PCI SIG) recently released an interim 0.71 version of the PCIe 3.0 specification that supports up to 8GTps. The PCI SIG aims to start testing products for compliance in early 2011, about a year later than originally anticipated.

The new speed grade will be needed to support adapter cards for the 40- and 100GbE standard recently approved by the IEEE. It will also be used for high-end graphics cards, next-generation Infiniband interconnects, flash drives and other applications that demand high throughput.

"I don't think we have lost any opportunities," said Al Yanes, president of the PCI SIG and a chip developer at IBM Corp in a meeting with press at the annual PCI SIG Developer's Conference.

"Our member companies are OK with this timeline," said Yanes. "40G Ethernet is not here yet, and is still being developed by our member companies," he said.

"It's a trial-and-error processthat's why we hate to give timelines," explained Ramin Neshati, chair of the PCI SIG's serial communications work group and a senior engineer at Intel Corp.

"One day we have one company with results saying we can meet the spec, and another day someone says, 'did you consider acoustics, or thermals or humidity and how these things impact the design,'" Neshati said. "It's a very lively environment where people come in with all sorts of data and some of it doesn't align, so we have to go back and find out why, find the mistake, align everyone and move forward," he added.

Issues behind the delay include the sophisticated equalization and encoding needed to support the maximum 8GHz data rate of the third generation of Express.

Encoding upgrade
The version 0.71 of the spec, released in early June, details changes needed in the training sequence to properly balance a DC transmission to derive a signal clock. It also makes it explicit engineers will have to use at least one tap of decision feedback equalization (DFE) in the receiver and three taps of continuous linear equalization in the transmitter.

Gennum Corp. announced in 2009 it is licensing silicon controller and PHY blocks for PCIe 3.0 that use five-tap DFE.


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