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A high-level synthesis methodology for complex FPGA

Posted: 25 Jun 2010 ?? ?Print Version ?Bookmark and Share

Keywords:complex FPGA? synthesis methodology? implementation VLCD?

This article describes the implementation of Virtual Line Crossing Detection (VLCD) on an Altera Stratix II FPGA and the methodology we used. Our primary challenge was to demonstrate a working video analytics algorithm on an FPGA within an extremely aggressive schedule of six weeks. On previous projects, we overcame similar challenges by using Catapult C Synthesis from Mentor Graphics to produce a hardware design from an existing C algorithm. Evaluation results from these projects have shown a 71 percent reduction in effort, compared to a manual RTL approach. This was due to a significant reduction in the implementation and verification effort.

VLCD is one of the video analytics algorithms used in video surveillance applications. It is used to detect and track animate and inanimate objects introduced into a predefined boundary.

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