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Silicon IPs enable increased SoC density

Posted: 02 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:silicon IP? Soc density? EDA?

Dolphin Integration SA has introduced an array of silicon IPs optimized for high density to allow designers to increase the density of their SoC by up to 10 percent.

The EDA company claimed that the 65nm High Density Panoply represents a complete solution for the whole logic design to address the cost reduction challenge at the architectural level.

The panoply includes single-port and dual-port RAMs, metal programmable ROMs, Register Files and standard cells.

It is designed for consumer and industrial applications with high fabrication volumes and low cost manufacturing requirements.

- Anne-Francoise Pele
EDA DesignLine

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