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Design software delivers low-power, low-cost FPGAs

Posted: 07 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? design tool? software? hardware?

The Lattice Diamond FPGA Version 1.0 design software provides as set of tools and a modern user interface to enable designers to more quickly target low power, cost sensitive FPGA applications.

Diamond will essentially replace the ispLEVER tools which Lattice Semiconductor Corp. will continue to support for FPGA design over the next 18 months while transitioning its FPGA customer base to the Diamond design environment. There are no changes to the ispLEVER Classic product, which targets CPLD and legacy FPGA devices.

Lattice has retained some of the features used in ispLEVER including an accurate power calculator, simultaneous switching output noise calculator, and the proven MAP and PAR FPGA implementation algorithms.

To improve 'what if?' design exploration Diamond software supports multiple design implementations with a design source being shared among implementations, or each implementation can have its own unique design source.

Different approaches can be tried to evaluate their effect on design size, cost, performance and power. Optimization options for logic synthesis and place and route are captured as a "strategy" that can be applied to any of the implementations.

Diamond software comes with a library of pre-defined strategies, and users can also create their own and add them to this library. A single strategy's settings can be updated, for example to an alternate PAR algorithm tuned for highly connected designs, and run against several unique implementations to determine if the results better meet the design goals for cost, power and performance.

A "run manager" can launch a user-selected set of implementations to be run through the flow, exploiting multicore processors, if available, to improve the elapsed time to final results.

Designers can manage their design view windows through the attach/detach feature. This feature allows the activation of many alternate concurrent design views across the available screen space, yet avoids the clutter that could result without advanced window management. Combined with the extensive cross-probing between Diamond Views, designers can investigate their design implementation's utilization and critical timing.

Also included to improve designer productivity is built-in HDL visualization and code checking saves time by quickly catching coding errors and improving design documentation. Using a timing analysis view navigation of the static timing results is eased and when timing constraints are revised, direct updates to timing analysis avoid the potentially significant time required to re-implement the design.

Diamond software also includes capabilities for scripting the design flow. Tool command language command dictionaries specific to the Diamond design environment are available for projects, netlists, HDL code checking, power calculation and hardware debug insertion and analysis.


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