Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Opinion: Tsunami to hit electronics shore

Posted: 08 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? chip design? verification?

There's a tsunami to the vast electronics ocean. EDA might well be able to catch the wavewith a little bit of savvy, ingenuity and engineering know-how.

Change is inevitable as design teams face shrinking resources, shorter timelines and mounting complexity. Every SoC designed today is not digital or analog but a combination of both. There really is no longer any digital design or analog design. We're entering an era of true mixed-signal SoCs, with DSPs, CPU/GPUs and analog blocks defining every design.

What's more, the investment community is taking notice. The semiconductor startup with the biggest chip is not always funded. It's the company designing a chip with an architecture that differentiates and almost always is now a mix of analog and digital that attracts attention these days. The most differentiated chip is capturing the wave of interest and that chip is based on a combination of analog and digital parts. Gone are the days when a semi startup could enter the market with a digital chip a few percent smaller in die size than the nearest competitor. In fact, the demand for mixed-signal chips has exploded, with the market growing from $2 billion in 1998 to more than $25 billion today.

EDA software provides great capabilities but is often behind the curve when it comes to supporting new and emerging technologies or finer technology process nodes. As the semiconductor industry moves to integrate analog and digital components, design gets more complex. Just consider:

??Designs are getting larger but design teams aren'tthey have to stay the same or have to get smaller to be profitable, while project schedules continue to compress.

?? While today completing one million instances on the digital side alone can take four to five days to, designers should be enabled to complete multimillion digital instances in a day for mixed signal designs to succeed.

??Ping Pong is fun for a game, not so much fun for taping out a chip. Designers must be able to close quickly even the toughest designs.

??Power reduction has reached critical proportions due to mobile devices, and has to be considered throughout the entire flow.

??Design reuse has to move from a buzz word to a method across digital and analog design.

??Verification has to move to correct-by-construction methods.

To enable designers to meet these challenges, the wall between analog and digital design must be dismantled. The EDA industry can help remove it by providing a solution to seamlessly mix the two signals.

What's currently available for integrated analog and digital design is error prone and time consuming. To implement these larger, more differentiated SoCs, such a solution needs to be more fully automated to offer design teams increased productivity, and deliver better performance and quality of results. A fully mixed-signal environment must have a strategic component for chip planning.

In addition to software for analog and digital design, the tool should offer a rich feature set of library (from I/Os, standard cells and analog block) characterization tools, chip finishing, physical verification and yield management. It's essential for mixed-signal SoC tools to leverage multithreading and multiCPU servers to cut turnaround time without compromising design performance. New high-capacity timing and extraction technology is needed to improve static timing analysis throughput with SPICE-level accuracy.

Take sign-off, for example. Static timing analysis tools in use today are about 15 years old with sequential runs for handling variability, leaving one to wonder about their capacity limitations or how fast and accurate they are.

This tsunami within the ocean of electronics is changing semiconductor design. There is no digital design, there is no analog design, but truly a mixed design in SoC. With it comes a tremendous opportunity for EDA. If EDA can catch the wave through the innovation of smarter, higher capacity tools for mixed-signal SoC design, it will truly be epic.

- Rajeev Madhavan
Chairman and CEO, Magma Design Automation Inc.





Article Comments - Opinion: Tsunami to hit electronics ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top