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EVG, IME join hands on 3D IC integration

Posted: 13 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:3D IC? wafer bonding? lithography? chip stacking?

EV Group (EVG) of Austria and the Institute of Microelectronics (IME) of Singapore signed a two-year agreement to cooperate on advancing 3D IC integration technologies. As part of the agreement, EVG will provide IME with process engineering support and access to its demo lab in Austria while IME will serve as a process hub for EVG's Asia-Pacific customer base.

IME deputy executive director Patrick Lo explained, "EV Group has provided IME with strong technology support to expand our research and development capabilities. The flexibility of their systems and the process expertise that EVG's team demonstrated enables us to ramp quickly and scale seamlessly."

The joint development will create a significant impact on IME's 3D IC R&D capabilities, particularly in wafer bonding, lithography and chip stacking for 200- and 300mm through-silicon via process development. Applications set for R&D projects include wafer spin and spray coating, chip-to-wafer bonding, wafer-to-wafer permanent bonding, temporary debonding and wafer cleaning. Endeavors will focus on coating thickness and uniformity control, bonding alignment accuracy control, impact of wafer characteristics on the bonding process and yield, bonding interface evaluation, process time optimization and material qualification evaluation on adhesives for temporary bonding, photoresist and permanent bonding.

EVG corporate technology development and IP director Markus Wimplinger commented, "This partnership with IME represents another step forward for EV Group in 3D IC research and development, and significantly expands our reach and presence in the Asia-Pacific region."

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