Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Uncertainty marks future of advanced lithography

Posted: 20 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:lithography? Semicon West?

An undercurrent of disquiet at Semicon West this week sprang from deep uncertainty in the roadmap for advanced lithography.

As with a royal succession, uncertainty in this vital area threatens the future with cost, chaos, and bloodshed. But despite brave pronouncements by vendors and users, it appeared that the industry was bracing for the worst: beset users buckled down for a hard time, and unlikely claimants marshaled their forces to press for a spot on the throne

Gregg Bartlett, GlobalFoundries Inc.'s senior vice president of technology and R&D, planted a brave banner on the field with his Wednesday (July 14) keynote, saying that the company would install a production-grade EUV lithography tool in 2012, and actually use it in production by perhaps 2014.

But much of the industry remains deeply skeptical. Symptoms of the uncertainly were visible in an afternoon session on advanced lithography.

Jongwook Kye, principal member of technical staff at GlobalFoundries, filled in some of the concerns that might have been obscured by Bartlett's flag-planting. Kye pointed out that lithographers were already working at numerical apertures far higher, and a k1 far lower, than were thought feasible a few years ago.

Even so, random patterns were nearly impossible to print. And lithographers are running out of options. Kye warned that the full cost of double-patterning was growing so high that EUV!should it's vastly expensive machines ever be available!was looking like a low-cost alternative. Still, he said, spacer-defined double patterning would probably be necessary on some critical!and sufficiently regular!layers.

But in general, Kye argued, there are no magic fixes. The way forward will be increasingly complex 193-nm lithography, made possible by unprecedented cooperation between technology and design teams.

"In the past, the link between technology developers and chip designers was only the process design kit," Kye said. "Now that is not enough. The two groups must sit together."

Technology teams must tell designers what features can actually be printed, Kye said. And designers must deliver layers that use only feasible patterns. In exchange, the technology team can deliver useful yields and improved performance, without having to wait for the end of the EUV rainbow, he said.

A starkly different view came from a purveyor of a technology that few semiconductor designers have been watching: nano-imprint. Ben Eynon, vice president of semiconductor business development at imprint equipment vendor Molecular Imprints Inc. (MII), argued that for NAND flash production at leading-edge geometries, his company's systems would soon be the best available choice.

Eynon cited calculations done at Toshiba suggesting that at an advanced process node the total cost of ownership for imprint would be half that of EUV, and a quarter that of double patterning. Those numbers depend on availability of a mask replicator, an imprinting device that creates many working imprint masks from one e-beam-written master.

Eynon said the replicator should ship by the end of 2010, and that speed for mask-inspection tools was sufficient to ensure an affordable flow of production masks.

The claim that imprint is near production viability for flash is rather startling. MII has already established itself in production of patterned media for disks. But conventional wisdom has held that the relatively high defect densities of the process!tolerable on disk platters!would give unacceptable yield for ICs. And certainly that is still the case for designs such as SoCs, where much of the circuitry has no redundancy.

But it appears that MII's work on the two primary defect sources!particle contamination and damage of the mask!has brought the defect density down to where NAND flash's powerful error correction can deal with it.

In summary, Eynon argued that when NAND production managers ran out of other alternatives, imprint would be ready to step in.

As delays and questions continue to plague EUV, and as the cost estimates for double-patterning continue to spiral, expect to see more managers like Kye taking highly pragmatic mixed-technology approaches, and drawing back-end design teams deeper into the complexities of process decisions.

And watch for radical ideas!mechanical imprint patterning, multi-electron-beam, and perhaps others!to opportunistically snap up critical layers on particular kinds of devices, where a radical idea might just seize the crown.

- Ron Wilson
EE Times





Article Comments - Uncertainty marks future of advanced...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top