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Taiwan maker demonstrates 3D vertical gate NAND device

Posted: 23 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:3D? NAND Flash? non-volatile memory?

Macronix International Co. Ltd, a provider of nonvolatile memory semiconductor solutions, reveals it has successfully made a 3D NAND Flash device using its patented barrier engineering (BE-SONOS) charge-trapping technology and 3D decoding architecture. The company claims that the device provides a successful path to the most scalable and most efficient 3D NAND flash.

In a paper, Macronix reports the fabrication and demonstration of the 8-layer, 75nm half-pitch, 3D vertical gate (VG) NAND flash using a junction-free BE-SONOS device. The BE-SONOS charge-trapping device provides both high reliability and simple structure suitable for 3D. At an equivalent 0.0014?m? cell size, the 3D VG NAND has shown no Z-directional interference, large read current, and 7V program window for multilevel cell operation.

"Traditional NAND flash will be facing technology barrier when it scales to below 2Xnm node" said C. Y. Lu, president, Macronix. "The 3D memory cell array structure has been proposed to be the most promising candidate for NAND Flash to shrink to below 1Xnm. Macronix's 3D memory research results based on our own BE-SONOS technology have set a new milestone for next generation NAND flash to meet high density capacity requirement."

The 3D cell technology stacks memory cells in three dimensions, making terabit NAND flash possible. Using 3D stacking, NAND flash may achieve higher data storage capacity and effectively lower fabrication cost without relying on advances in lithography technology. Thus, some memory manufacturers have invested in 3D research recently.

Several 3D NAND flash structures have been proposed, such as P-BiCS(Pipe-shaped Bit Cost Scalable), TCAT(Terabit Cell Array Transistor), VSAT (Vertical Stacked Array Transistor) and VG. However, in a 3D structure interference (cross talk) occurs between neighboring cells in the same plane and between vertical neighbors in adjacent planes. This has become a new challenge in addition to the conventional Moore's law scaling issues.

Through detailed analyses on scalability, reading current (which determines read speed performance) and cross talk, Macronix selected the VG architecture. Simulation shows this structure could be scaled to 25nm node in a 3D array, providing density far beyond conventional 2D NAND flash.

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