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Alliance pushes GigaChip interface

Posted: 26 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:GigaChip Alliance? serial interface? SerDes?

The GigaChip Alliance has been launched, reports MoSys Inc. MoSys is joined by Altera and NetLogic Microsystems as the founding participants who will collaborate on expanding the GigaChip Interface.

Announced by MoSys in February 2010, the GigaChip Interface is a board-level, open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications in next generation high-performance networking, computing and storage systems. The alliance will also develop industry-wide open interoperability standards and tools to accelerate the adoption of serial chip-to-chip based system designs.

The GigaChip Interface is a short-reach, low-power serial interface, which enables highly efficient, high-bandwidth, low-latency performance not achievable using currently available serial protocols. MoSys believes the GigaChip Interface represents the next breakthrough in chip-to-chip communications using differential SerDes technology. A 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, which represents a bandwidth density performance increase of 4 times, while reducing system power and interface costs 2- 3 times. Such bandwidth density increases will be required to realize line cards with aggregate throughput beyond 100G, a necessity in future high end networking systems. The GigaChip Interface has adopted the open CEI-11 electrical transport standard making use of this existing electrical ecosystem in order to shorten time to market for the introduction of next generation system designs. Through the GigaChip Alliance, companies are enabling an entirely new class of low-cost, high-speed, high-performance systems in networking, computing and storage markets.

"We welcome the performance and efficiency that the GigaChip Interface will provide our FPGA customers," commented Arun Iyengar, senior director, communications business unit, Altera. "We are pleased to join the GigaChip Alliance so that we can help drive the evolution of serial chip-to-chip communications technologies, and we plan to support the GigaChip Interface in our FPGAs."

Chris O'Reilly, VP of marketing at NetLogic noted, "The GigaChip Alliance is helping to address an important system-level need for a high-bandwidth low-latency interface."

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