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Design flow optimizes partial reconfiguration FPGAs

Posted: 29 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? design software? clock gating?

The fourth generation of Xilinx Inc.'s partial reconfiguration design flow is available, the company announced. It also reported an improvement to its intelligent clock gating technology that delivers a 24 percent reduction in dynamic block-RAM (BRAM) power consumption in Virtex-6 FPGA designs.

Designers can download the ISE Design Suite 12.2 to take advantage of an easier-to-use, intuitive partial reconfiguration design flow and take steps to reduce power consumption and reduce overall system costs. It also offers a low-cost simulation solution for the embedded design flow.

"As systems become more complex and designers are asked to do more with less, the adaptability of FPGAs, in addition to their inherent reprogramability, has become a critical asset," said Tom Feist, senior marketing director, ISE Design Suite. "Xilinx FPGAs have long supported partial reconfiguration and the flexibility to perform on-site programming and re-programming. Today, however, the severity of the constraints on cost, board space and power consumption requires exceptionally efficient and economic design strategies to compete, which is why we've made the design flow easier."

Partial reconfiguration enables on-the-fly flexibility that can dramatically expand the capabilities of a single FPGA. While operational, designers can reprogram regions of the FPGA with new functionality without compromising the integrity of the applications running in the remainder of the device. For example, customers developing wired optical transport network solutions can achieve multiport multiplexer/transponder capabilities using 30-45 percent fewer resources, whereas Software Defined Radio solutions can dynamically exchange communication waveforms at the same time as other waveforms continue to operate without interruption and the need for bigger or additional components. Partial reconfiguration also enables designers to manage power consumption by swapping out high-power consuming functions for more power-efficient functions when the highest performance is not required.

Xilinx has made its fourth generation partial reconfiguration easier to use with a more intuitive design flow and interface. This includes an improved timing constraint and timing analysis flow, automatic insertion of proxy logic to bridge static and reconfigurable partitions, as well as full-design timing closure and simulation capabilities. ISE Design Suite 12 enables designers to target Virtex-4, Virtex-5 and Virtex-6 devices for partial reconfiguration applications.

Smart clock-gating

To help customers make their designs more power efficient, Xilinx enhanced its Intelligent Clock-Gating technologywhich it obtained through the acquisition of PwrLite Inc. in 2009to enable the lowering of BRAM dynamic power. Through a unique set of algorithms, the ISE Design Suite can automatically neutralize unnecessary logic activity. This is a primary factor behind power dissipation, as it enables power optimizations that were not applied at the RTL level to be implemented downstream after synthesis, thereby reducing overall dynamic power consumption by as much as 30 percent.

Starting in ISE Design Suite 12.2, the intelligent clock-gating optimization will also reduce power for dedicated RAM blocks in either simple or dual-port mode. These blocks provide several enables: an array enable, a write enable and an output register clock enable. Most of these power savings will come from using the array enable.

Simulation support

ISE Design Suite 12 offers the ISE Simulator (ISim) through the Xilinx Platform Studio (XPS) and Project Navigator tools, enabling embedded designers to take advantage of the mixed language (VHDL and Verilog) simulator integrated with the ISE Design Suite. The new version of ISim has several new productivity-enhancing features, including automatic detection and listing of design memories for viewing and editing. This new Memory Editor enables designers to explore what-if scenarios using a graphical way to force a value or pattern on a signal without needing to recompile the design. ISE Design Suite 12 also makes it possible for designers to navigate to HDL source from the waveform viewer.

ISE Design Suite 12 is rolling out in phases with intelligent clock gating for Virtex-6 FPGA designs already shipping now with the 12.1 release on May 3, 2010, partial reconfiguration for Virtex-6 FPGA designs starting in the 12.2 release, and AXI4 IP support to follow in the 12.3 release. The ISE Design Suite 12 works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.

ISE Design Suite 12 software features an average of 2X faster logic synthesis and 1.3X faster implementation run times for large designs than previous versions and an improved embedded design methodology. It is available for all ISE Editions and list priced starting at $2,995 for the Logic Edition. Fourth generation Partial Reconfiguration can be purchased as an option and is bundled with two days of onsite training.





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