Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Embedded
?
?
Embedded??

Optimizing power in SoC designs

Posted: 28 Jul 2010 ?? ?Print Version ?Bookmark and Share

Keywords:power optimization? SoC design? efficient power?

Growing energy costs and the "green" revolution are driving designers to reduce the power consumption of SoCs used in today's electronics systems. The most common method for optimizing power in these complex circuits is through clock gating.

Clocks that toggle unnecessarily are key contributors to dynamic power consumption in flip flops, related downstream logic and in the clock network. Clock gating reduces dynamic power consumption by eliminating unnecessary clock toggling without affecting the functionality of the original design.

The goal of the designer, then, is to maximize the average clock-gating efficiency (CGE) of a design. CGE is defined as the percentage of time that registers in a design are clock-gated for a given stimulus or switching activity.

Maximizing CGE can be easier said than done. Designers may be able to make an "educated guess" about where to insert clock gating. However, once the RTL modifications are made and RTL power analysis is run, the results may come back positivepower went down or they may be negativepower remained largely unchanged or even increased after the changes.

Unfortunately, though, RTL power analysis tool results may not be accurate. Precise analysis requires synthesizing the design and performing the power analysis at the gate levela long and tedious process. In the often brief time allotted for power optimization during a project, design teams may only be able to complete one or two iterations, severely limiting power optimization.

Current methods employed by designers for optimizing power are inefficient and unproductive, making it difficult to know when a design is fully power optimized. The solution is to use a power optimization tool that can be run in a regression mode, which creates a feedback loop to designers and project management.

This will ensure that the optimizations and hints provided by the tool are appropriately utilized according to the project goals and timelines. A power regression flow would allow designers to gauge the thoroughness of power optimization for a design, ensuring that the design is power optimized to the greatest extent possible.

View the PDF document for more information.





Article Comments - Optimizing power in SoC designs
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top