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Shorten test time with package-based MBIST strategy

Posted: 02 Aug 2010 ?? ?Print Version ?Bookmark and Share

Keywords:test time? MBIST strategy? ASIC test?

Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application.

Test mode usually accompanies memory built-in self test (MBIST) mode, which goes through all the bit-cells for all memory banks in a design. Depending on the implementation of BIST module, we may have parallel and serial access capabilities to test the same. This test is performed at wafer level and package level. We usually have multiple packages available for SoC, which has a different number of power pads available.

Nowadays, MBIST controllers have capabilities of controlling multiple memory banks in parallel or in a serial fashion. These capabilities can be exploited to get a customized pattern suit for each package and wafer level separately.

An SoC is configured for multiple package configurations, which have different functionalities available for the customer. This means that the number of power pads available for each of the package would be different. A 48-pin package may have only two pairs of VDD and VSS, whereas same die going into 100-pin package can provide even four or five pairs of power and ground pins.

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