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Low-power, high-speed ADCs comply with JESD204A

Posted: 02 Aug 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? analog-to-digital converter?

Analog Devices Inc. (ADI) has started to sample a pair of low-power, high-speed 14-bit ADCs (analog-to-digital converters) that incorporate the JESD204A data converter serial interface standard.

The JESD204A standard was developed to allow designers of high-speed communications and data acquisition systems to extend transmission lengths while improving signal integrity and simplifying printed-circuit board layout. The AD9644 dual and AD9641 14-bit 80 mega samples per second (MSPS) ADCs use half the power of competing products and 25 percent less board area, according to ADI.

The AD9644 consumes 423 mW at 80msPS and features a multi-stage, differential-pipelined architecture with integrated output error correction logic. At 70MHz and 80msPS, the AD9644 achieves an SNR (signal-to-noise ratio) of 73.7 dBFS and an SFDR (spurious-free dynamic range) of 92 dBc.

The JESD204A industry serial interface standard reduces the number of data inputs/outputs between data converters and other devices, such as FPGAs. Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important for a range of high-speed applications, including portable instrumentation, ultrasound equipment, radar, wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA), and software-defined radios.

The AD9644 is available in a 48-lead LFCSP (7 mm x 7 mm) and is specified over the industrial temperature range of -40C to +85C.

For 1,000-unit orders, the AD9644 is $37 each, and the AD9641 is $26.35. Samples are now available.

- Ismini Scouras
EE Times

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