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Microprocessor delivers high-performance connectivity

Posted: 03 Aug 2010 ?? ?Print Version ?Bookmark and Share

Keywords:multiple embedded application? network-on-chip? system-on-chip? microprocessor?

STMicroelectronics has just introduced a new embedded microprocessor that pairs up two ARM Cortex-A9 cores with a DDR3 memory interface. Manufactured through ST's low-power 55nm high-speed CMOS process technology, the SPEAr1310 renders high computing power and customizability for multiple embedded applications together with a high level of cost competitiveness offered by system-on-chip (SoC) devices.

The new microprocessor combines the unparalleled low power and multi-processing capabilities of the ARM Cortex-A9 processor core with innovative Network-on-Chip (NoC) technology. These dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (for industrial worst-case conditions) for 3000 DMIPS equivalent.

General Manager of STMicroelectronics' Computer Systems Division, Loris Valenti says that the SPEAr1310 has an innovative architecture and a powerful feature set, currently at the leading edge of the embedded processor market, which enables an unprecedented mix of cost competitiveness, performance and flexibility.

Armed with an integrated DDR2/DDR3 memory controller and a full set of connectivity peripherals, including USB, SATA and PCIe (with integrated PHY), in addition to a Giga Ethernet MAC, ST's SPEAr1310 microprocessor enables high-performance embedded-control applications across market segments from communication and computer peripherals to industrial automation. Its cache memory coherency with hardware accelerators and I/O blocks increases throughput and simplifies software development. The Accelerator Coherency Port (ACP), coupled with the device's NoC routing capabilities, responds to the latest application requirements for hardware acceleration and I/O performance. ECC (Error Correction Coding) protection against soft and hard errors on both DRAM and L2 Cache memories dramatically improves the MTBF for enhanced chip reliability.

Samples of the SPEAr1310 are now available upon request for evaluation and prototyping.





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