New player innovates in FPGA-based prototyping

A light may be shining at the end of the tunnel for SoC design teams suffering the drag of hardware and software integration using pre-silicon prototypes. A new company that just came out of stealth mode today, InPA Systems Inc., claims that it has developed a technology that compresses integration time from weeks into days.

InPA Systems expedites prototyping by integrating and automating multiple steps in the process, and by enabling simultaneous debugging. Prior to this technology, engineers must capture and debug one FPGA at a time.

InPA Systems is integrating the RTL simulation and FPGA prototype environments and automating a critical portion of the "bring up" that verifies that the mapping of the RTL code into the multiple FPGAs correlates to the original RTL code. They are also integrating the RTL code and FPGA prototype environment so that engineers can debug in their RTL code while accessing their captured faulty conditions with full visibility. The automation here is to cross-link the RTL code with the captured faulty condition and to expand full signal visibility around the faulty condition.

Furthermore, InPA Systems is also integrating the software and hardware debug environments so that engineers can catch issues easier when integrating both HW/SW in the FPGA prototype environment. The automation here enables full system debug with Active Debug (patent pending) technology to cross-trigger between HW/SW.

"We use FPGA prototypes extensively for our SoC design projects as it has become an essential hardware verification and software application validation tool," said Dr. Gene Chuang, SoC Technical Director, Wireless Broadband Technology Division of Industrial Technology Research Institute (ITRI) in Taiwan. ITRI, which is one of InPA's beta sites, plans to incorporate InPA into their debug methodology when Active Debug is released.

"While FPGA prototypes are popular, they are also difficult to use. We are excited to see that the InPA Systems Active Debug including full visibility technology will make our FPGA prototype verification environment even more powerful and easy to use," Chuang shared.

According to InPA, Active Debug is the first solution to enable users to gain control when running the design, at speed, in the validation process, allowing them to capture complex scenarios in the FPGAs and analyze system faults with full signal visibility. Current passive debug technology requires a highly iterative and mostly, blind process that requires the user to continually guess where system faults might be located on the SoC.

The new company is in the process of building its partnership ecosystem with EDA and FPGA prototype providers and key distribution companies who are focused on the rapid prototype market segment, so that the company can offer customers a completely integrated product. These partnerships will be announced over the next few months. The company expects its first product to be available in 4Q 2010.

At the helm of this company are logic and emulation authority Thomas Huang, chairman and CTO and verification expert Michael Chang. Both have founded a number of startups. Huang is probably best known as a co-founder and the CTO of PiE Design Systems, a pioneering logic emulation company. He joined Quickturn when that company acquired PiE. He holds nine patents covering various aspects of logic emulation.

Chang is the co-founder, CEO and president of Verplex, a formal verification company that was acquired by Cadence. He spent a number of years at Cadence as VP and GM of its formal verification group there. Chang also founded DFT vendor Checklogic that was acquired by Mentor Graphics and holds a patent in equivalence checking.