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HLS tool allows designers to focus on ASIC differentiation

Posted: 09 Sep 2010 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC? high-level synthesis? HLS?

Mentor Graphics Corp.' Catapult C tool for the high-level synthesis (HLS ) of next-gen ASICs has been deployed by Toshiba Information Systems .

With Catapult C, Toshiba Information Systems explained that it spends less time working on the implementation details and more time on differentiating its products by creating sophisticated algorithms and adjusting the hardware architecture for specific design and technology objectives.

Catapult C, Mentor explained, is a high-level synthesis solution offering combined support for both SystemC and ANSI C++ input sources. It automatically generates control and algorithmic RTL multi-block designs from pure ANSI C++ and SystemC sources, and this process empowers designers to quickly achieve fully optimized and error-free hardware implementation.

"Our design teams have become quite familiar and comfortable with using the Catapult C tool for design exploration and for creating RTL code from the C-based functional descriptions," commented Akiyoshi Ohguro, Group Leader, LSI Design Center Dpt.1, LSI Solutions Division, Toshiba Information Systems (JAPAN) Corporation.

Ohguro continued, "Our last project was fairly complex in nature, but the Catapult C tool made the process of implementing and verifying our functionality very manageable. Starting from high-level C++ code, we were able to explore various implementation options for the 8X8 matrix of eigenvalue decomposition algorithm that is at the heart of our FocusNavi product. We were able to improve the overall latency performance by a factor of five while keeping the same frequency (100MHz) and area (50K ASIC gate count). This was possible all because of high-level synthesis."

- Anne-Francoise Pele
EE Times

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