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1GHz programmable DSP core touts energy efficiency

Posted: 13 Sep 2010 ?? ?Print Version ?Bookmark and Share

Keywords:programmable DSP? silicon intellectual property?

CEVA Inc., the licensor of silicon intellectual property (SIP) platform solutions and DSP cores, has just introduced the CEVA-X1643, a highly-energy efficient, 1GHz DSP core designed to pump-up overall chip performance for a broad range of applications.

Its target applications include wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 utilizes the architectural efficiency and mature software development environment of the existing CEVA-X family of DSP cores and boasts a number of major enhancements, including: support for an advanced data cache and tightly coupled memory architecture, streamlining software integration and software porting from other DSP platforms; memory management support simplifying RTOS and multi-tasking; integrated Power Scaling Unit (PSU) enabling a highly energy-efficient architecture; configurable 64/128 bit AXI system busses supporting high memory bandwidth; inherent support for seamless migration from TI C6x C-code; over 1GHz DSP performance using standard 40nm process technology at worst-case conditions. It is fully compatible with all CEVA-X products.

The CEVA-X1643 DSP offers a Very Long Instruction Word (VLIW) architecture along with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, which incorporates the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. With a well-balanced pipeline, the CEVA-X1643 can operate at over 1GHz in chips implemented at the 40 nm technology node.

Likewise, to ensure target performance is met in a real-life system, the device is equipped with a high performance Advanced eXtensible Interface (AXI) based memory sub-system supporting: configurable AXI bus width, parallel read-and-write transactions, read after write transactions and other advanced capabilities. The use of must-have industry standard system buses together with a fully cached CEVA-X processor empowers high performance, shorter design cycle and easy integration into the target SoC.

The CEVA-X1643 DSP core also offers an innovative Power Scaling Unit (PSU). This provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches. The PSU supports multiple operational modes ranging from full operation, debug bypass, memory retention, to complete power shut-off (PSO). Further, the AXI full duplex busses buses provide low-power capabilities, such as the ability to shut down when no data traffic is present. The CEVA-X1643 offers significant energy savings for both battery-operated and stationary devices, a critical and significant factor in an increasingly green-energy conscious world.

Furthermore, the device supports easy migration from off-the-shelf DSP chips to integrating DSP cores into customer SoC designs. The combination of a compiler-friendly 8-way VLIW and SIMD architecture, advanced data cache architecture and memory management capabilities allows licensees to efficiently migrate legacy code and ensures similar DSP performance levels at a significantly lower price.

Finally, the CEVA-X1643 DSP core is supported by CEVA-Toolbox, a software development, debug, and optimization environment which provides near-optimal system performance to be attained using standard C source code. CEVA-Toolbox has an Application Optimizer tool, allowing application developers to easily develop software purely in C-Level, thereby doing without time consuming, hand-written assembly coding. The end result is a significantly better overall performance and a shorter design cycle for SoC designs. As noteworthy example, the Application Optimizer was used to implement the AMR-NB (Adaptive Multi Rate-Narrow Band) vocoder on the CEVA-X1643 DSP core and required only 18MHz when compiled out-of-the-box (for worst-case frames and streams).

The CEVA-X1643 is now available for licensing.





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