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Transceiver deployed on 28nm FPGA

Posted: 23 Sep 2010 ?? ?Print Version ?Bookmark and Share

Keywords:transceiver? programmable logic? PL? FPGA?

Altera Corp. unveils a 28nm transceiver test chip that it presents as a prototyping platform to deploy 28Gbit/s transceivers on 28nm FPGAs. The 25Gbit/s performance more than doubles what transceivers can offer in current FPGA solutions, and surpasses the abilities of competitive ASSPs.

The 28nm transceiver test chip provides insight into how high-performance transceiver designs behave on TSMC's 28nm high-performance (HP) process.

Results of the test chip let Altera develop and apply optimization techniques for power, jitter and link performance in the production tape-out of Stratix V FPGAs featuring 28Gbit/s transceivers. These FPGAs are targeted to applications that require very high performance at fixed cost and power budgets, such as military communications, optical transmission networks and emerging test equipment systems.

A video demonstration of the 28nm transceiver test chip running a pseudo-random bit pattern at 25Gbit/s is available on Altera's website at The video presents transmit and receive eye diagrams across a 10GBASE-KR backplane running at 10.3Gbit/s.

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