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ChipMOS reveals expansion plans for 12in wafer gold bumping

Posted: 07 Oct 2010 ?? ?Print Version ?Bookmark and Share

Keywords:wafer? gold bumping?

ChipMOS Technologies announced the expansion of its wafer gold bumping capabilities in Taiwan into the 12in high-performance gold bumping production.

ChipMOS currently projects facility and equipment setup completion by the end of 2010. The planned production line will be ready for production (with a capacity of about 4,000 wafers per month), on top of the company's 8in/6in gold bumping capacities, which are the current mainstream in driver IC manufacturing. By the end of Q3 2011, the 12in gold bumping capacity would increase up to about 10,000 wafers per month.

Chairman and CEO of ChipMOS, S.J. Cheng says, "We believe this added capacity will better enable us to capture business opportunities in high resolution mobile display product segment [such as those used by smartphones]. As an added bonus, we will also be able to utilize the 12in wafer gold bumping line for 8in wafer gold bumping production in order to address anticipated 8in capacity shortage. Importantly, since this line expansion was already factored into our capex plans as discussed in the most recent investor conference call, it will not result in any increase to our budget."

The company's investment in 12in gold bumping capability is aimed to answer customers' needs to adopt 12in wafer manufacturing for next generation, one-chip-solution display driver products, which are primarily used in small display panels for mobile applications, including smartphones. The resolution has increased significantly in small display panels, necessitating that the density of integrated buffer frame memory in the one-chip-solution display drivers be increase proportionally to accommodate the multi-functionality of the IC.

The final outcome is a significantly enlarged die size of the driver IC. By leveraging the 12in wafer manufacturing technology, the display driver die size is kept small by migrating into finer geometry, at the same time decreasing manufacturing costs per chip via throughput enhancement. Additionally, ChipMOS is also looking at upgrading its current 8in RDL (Re-Distribution Layer) capability into 12in along with this capacity expansion, and providing more MCP (Multi-Chip Package) assembly flexibilities for mobile/niche DRAM or flash customers.





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