Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Place and route system increases design variability

Posted: 25 Oct 2010 ?? ?Print Version ?Bookmark and Share

Keywords:license? graphics? GPU? place and route system?

Mentor Graphics' Olympus SoC place and route system has been licensed by Nvidia Corp. for its high performance graphics processors. The company said it has used the system on multiple GPU tapeouts, outlining the overall quality of results and design schedule savings.

Mentor claimed that its Olympus-SoC place and route system addresses the performance, capacity, time-to-market, and variability challenges of advanced digital IC physical design. It optimizes IC designs for variations in lithography, process corners, and design modes to deliver the best quality of results for timing, power, signal integrity and die size.

Product features include the patented Multi-CornerCMulti-Mode (MCMM) optimization during all design steps; fast routing with full 65nm and 45nm rule support; sign-off quality timing analysis and optimization; extremely fast and accurate, on-the-fly parasitic extraction; floorplanning, rapid design feasibility and constraint debugging; best-in-class, CTS-aware standard cell and macro placement; industry's first MCMM CTS for robust, low-power clock trees; MCMM SI to concurrently compute delay shift and glitch for any number of mode/corner scenarios in a single pass; advanced physical synthesis with built-in OCV and CPPR; and it handles multi-million gate designs hierarchical or flat with faster runtimes.

- Anne-Francoise Pele
EE Times

Find related content:
??-?company/industry news
??-?new products
??-?technical papers
??-?application notes

Article Comments - Place and route system increases des...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top