Ricoh licenses DeFacTo's DFT solution
Keywords:EDA? design for test? DFT? verification?
The HiDFT-Signoff solution enables scan logic insertion at RTL. It lets designers create a high-level design for test signoff methodology, closing the gap between RTL and DFT. It allows early identification of test issues and enables new pre-synthesis design and DFT verifications.
Ricoh indeed explained that the system has enabled the company to detect key testability issues and to improve test coverage early at RTL level. It helps move the DFT flow from gate-level to RTL level and allows accurate test coverage evaluation at RTL.
It also allows a full RTL interoperability with mainstream ATPG, test compression tools and synthesis tools. Then, the simulation process of ATPG test vectors could be moved to RTL "with a very significant speedup."
- Anne-Francoise Pele
EE Times
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