Cadence maps out design tool development strategy

Cadence Design Systems Inc. has sketched out a strategy for an end-to-end flow of silicon and software design tools. Part of the company's EDA360 campaign, analysts say that the ambitious move has many gaps to fill to bring the concept to reality.

Cadence outlined functional enhancements it will make to current and future products to provide the design tool integration it targets. For example, the tools will let engineers create an abstract representation for system-in-package and 3-D chip stacks to link package and chip design tools. It also promised new links between logic design, verification and manufacturing tools.

Cadence has acquired tools for virtualization and systems prototyping to expand beyond its traditional business in silicon design tools.

Once the undisputed leader in software tools for designing chips, Cadence is now vying with Mentor Graphics at second place behind archrival Synopsys that has claimed the top spot, according to EDA consultant Gary Smith.

Smith said the EDA360 vision is ambitious, but Cadence has several gaps to fill in its current silicon design flow. It has yet to deliver on its goal of creating an integrated suite of system and silicon design tools, he said.

Lip-Bu Tan, CEO, Cadence, said the company is focused on top technical challenges such as integrating hardware and software design and delivering low-power analog and mixed-signal design tools. The tools will help speed time-to-market, he said.

"We can no longer wait for hardware availability to start working on system design and even verification," said John Bruggeman, chief marketing officer, Cadence.

Standards setting
Bruggeman said Cadence will participate in creating standards for software models that describe full systems and can be run on a virtualization platform and modified with tools Cadence will supply. The platform will use a common data model and kernel to support the very different needs of software and hardware designers, he said.