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Asymmetrical dual-core digital signal controller architecture launched

Posted: 03 Nov 2010 ?? ?Print Version ?Bookmark and Share

Keywords:flash? architecture? algorithm? encoder? controller?

NXP Semiconductors N.V. has unveiled the world's first asymmetrical dual-core digital signal controller architecture featuring ARM Cortex-M4 and Cortex-M0 processors.

The LPC4000 family offers a single architecture and development environment for DSP and MCU applications. NXP said the dual-core architecture and unique configurable peripherals in the LPC4000 allow customers to develop a wide range of applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories and embedded audio.

NXP LPC4300 assymetrical dual-core digital signal processor

The LPC4000 family, which will be on display at Electronica 2010 in Munich and at ARM TechCon in California, is ideal for microcontroller designers seeking more efficient means of tackling math-intensive algorithms, DSP designers who need a more robust set of peripherals, and those who would like to upgrade from an existing DSC processor.

Among the key features of the asymmetrical dual-core digital signal controller architecture are an optimized 256-bit wide flash memory architecture, a state configurable timer, an SPI flash interface, a serial GPIO interface, a 32KB ROM containing boot code and on-chip software drivers, AES-128 decryption (and encryption in some members of the family), eight-channel general-purpose DMA controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor control PWM and quadrature encoder interface, four UARTs, two Fast-mode Plus I(2)C, I(2)S, two SSP/SPI, smart card interface, four timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256B of battery powered backup registers, and up to 146 general purpose I/O pins.

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