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FPGAs/PLDs??

65nm flash platform pushes out antifuse

Posted: 12 Nov 2010 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? 65nm flash platform? LUT architecture?

Kapusta said the move to 65nm flash has been in the works for over two years. Two years ago, Actel announced its intention of working with UMC on the 65nm embedded flash process, he said.

The firm choose to skip the 90nm node and "put all its eggs in the 65nm basket" because "we couldn't afford to do both and we needed to take that really big step to 65nm," Kapusta said.

Microsemi also offered a sneak peek at the next generation radiation tolerant (RT) flash-based SoCs. The fourth generation RT FPGAs will feature up to 20 million gates, offering a larger array of flip-flops, memory and hardened embedded IP cores, according to the company. The devices will include DSP blocks, PLLs and high speed interfaces (such as SpaceWire, DDR2/3, PCI Express) to get data on and off chip quickly and efficiently, the company said.

Microsemi also announced that Fusion mixed-signal FGPAs are now available with 100 percent temperature screening from -55C to +100C, enabling the company to market the devices to the military, avionics, and defense industries.

- Dylan McGrath
EE Times

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