PCIe Spec 3.0 doubles interconnect bandwidth

The PCIe Base 3.0 specification has been announced by the PCI-SIG. The I/O technology includes a 128-bit/130-bit encoding scheme and a data rate of 8GTps, doubling the interconnect bandwidth over the PCIe 2.0 specification. PCIe 3.0 technology also maintains backward compatibility with previous PCIe architectures. Possible topologies include servers, workstations, desktop and mobile personal computers, embedded systems and peripheral devices.

Based on the data rate rate of 8GTps it is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1GBps in one direction on a single-lane configuration and scale to an aggregate approaching 32GBps on a sixteen-lane configuration, according to the PCI-SIG.

The specification integrates several enhancements to the protocol and software layers of the architecture, such as data reuse hints, atomic operations, dynamic power adjustment mechanisms, latency tolerance reporting, loose transaction ordering, I/O page faults and other extensions in support of platform energy efficiency, software model flexibility and architectural scalability.

"Each new version of the PCIe spec has doubled the bandwidth of the prior generation," said Nathan Brookwood, research fellow at Insight 64, in a statement issued by PCI-SIG. "The latest group of PCIe architects and designers drove the standard forward while maintaining complete backward compatibility for Gen 1 and Gen 2 devices. Rarely has a standard advanced so non-disruptively through three major evolutionary cycles."

- Peter Clarke
EE Times

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