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Connect FPGA to ADC, DAC

Posted: 24 Nov 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Virtex-6? low-voltage differential signaling?

Here's a guide on how to use the dedicated deserializer (ISERDES) and serializer (OSERDES) functionalities in Virtex-6 FPGAs to interface with analog-to-digital converters (ADCs) that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters (DACs) that have parallel LVDS inputs.

Common ADCs have a resolution of 12, 14, or 16 bits. Typically, multiple converters in a single package are translated into multiple serial data channels. These converters can be used in two modes: 1-wire and 2-wire. The ADC Interface section provides a possible solution for both modes. High-speed DACs, however, have one or two (multiplexed data) parallel LVDS input ports. Generally, each interface port has a bit width equal to the

resolution of the DAC.

This application note by Xilinx provides a basic interface solution for these type of connections.

View the PDF document for more information.





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