Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Embedded
?
?
Embedded??

Superscalar CPU executes two threads at once

Posted: 25 Nov 2010 ?? ?Print Version ?Bookmark and Share

Keywords:broadband? video? SoC?

Broadcom has revealed a new MIPS-compatible CPU for its broadband SoCs. Unveiled in an exclusive article published in the Microprocessor Report, the BRCM 5000, also known by its code-name Zephyr, is the newest chip developed by Broadcom under an architecture license from MIPS.

According to Dan Marotta, executive VP and general manager of the broadband communication group, Broadcom, the CPUs have been a secret weapon for the company, with sales of products using the Broadcom-designed CPUs generating more than $2 billion per year in sales.

The BRCM 5000 is a superscalar CPU that executes two threads at once. The design is entering production in 40nm G technology at a clock speed of 1.3GHz. With a rating of 3,000 Dhrystone MIPS, the CPU is suited for high-end STBs, DTVs, DOCSIS 3 cable modems and other consumer applications. It appears in products such as the BCM7420.

CPU lineage
It's has been ten years since the company shipped its first DSL chip with an internally designed CPU, now known as the BRCM 3300 core. This CPU, which the company still uses today, measures less than 1mm2 in 40nm CMOS, including cache, making it suitable ideal for low-cost products such as ADSL chips. It uses a six-stage pipeline to achieve clock speeds of 700MHz in 40nm G. It generally uses 32KB of instruction cache and 16KB of data cache, although the synthesizable design can be configured in multiple ways. The small data cache is optimized for broadband applications, in which most of the data is streamed through the processor and doesn't need to be cached.

The company next developed the BRCM 4355 CPU for VDSL and other higher-performance modems and STBs. This chip is designed as a dual-CPU module in which the two CPUs share a single data cache. This structure was originally designed to simultaneously support two OS--for example, a RTOS to process broadband data and Linux to provide a user interface. The shared 32KB data cache simplifies synchronization and avoids wasting cache on streaming broadband data. Each of the two CPUs is similar to the BRCM 3300 in speed and issue rate.

A more recent version of this CPU, called the BRCM 4380, expands the shared data cache to 64KB and adds an exclusive 128KB level-two cache. This design also adds DSP extensions and a floating-point unit to accelerate 3D user interfaces in STBs. This CPU, which achieves a speed of 700MHz in 40nm G, appears in Broadcom products such as the BCM7400, BCM7405, and BCM7335 STB processors.


1???2?Next Page?Last Page



Article Comments - Superscalar CPU executes two threads...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top