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Understanding source-synchronous SerDes

Posted: 02 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? Spartan-6? 8-bit?

Spartan-6 devices from Xilinx contain input SerDes and output SerDes blocks. These primitives simplify the design of serializing and deserializing circuits, while allowing higher operational speeds. This application note tackles how to efficiently use these primitives in conjunction with the input delay blocks and phase detector circuitry.

Each Spartan-6 FPGA input/output block contains a 4-bit input SerDes and a 4-bit output SerDes. The SerDes from two adjacent blocks (master and slave) can be cascaded to make an 8-bit block. This gives the possibility of SerDes ratios from 2:1 to 8:1 on both output and input for both single and double data rate I/O clocks.

View the PDF document for more information.

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