Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Create wider memory interface with MCB

Posted: 06 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Memory Controller Block? Spartan-6? Xilinx?

The memory controller block (MCB) is a dedicated embedded multi-port memory controller that simplifies the task of interfacing Spartan-6 devices to DDR3, DDR2, DDR, and LPDDR memories. Spartan-6 devices contain two to four MCBs, each of which can implement a single component interface to a 4-bit, 8-bit, or 16-bit memory. Some applications with higher memory bandwidth or density requirements benefit from using memory interfaces wider than the 16-bits offered by a single MCB.

This application note describes how to merge the operation of two or more MCBs to implement effective 32-bit or wider memory interfaces. Both MCBs must be in a single-port configuration mode. This application note and reference design by Xilinx does not support merging MCBs configured in the multi-port configuration mode. The associated reference design has been verified in hardware, and analyzed for both performance and device utilization.

View the PDF document for more information.

Article Comments - Create wider memory interface with M...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top