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FPGAs/PLDs??

Interface FPGA with 3.3V system

Posted: 08 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? Virtex-6? 3.3V I/O standards?

This application note by Xilinx discusses methodologies for interfacing Virtex-6 devices to 3.3V systems. It covers input, output, and bidirectional busses, as-well-as signal integrity issues and design guidelines. All the devices in the Virtex-6 family are compatible with and support 3.3V I/O standards.

The Virtex-6 FPGA I/O is designed for both high performance and flexibility. Each I/O is homogenous, meaning every I/O has all features and all functions. This high-performance I/O allows the broadest flexibility to address a wider range of applications. A range of options can be deployed to interface Virtex-6 FPGA I/O to 3.3V devices.

View the PDF document for more information.





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