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SERDES Framer Interface Level 5 for FPGA

Posted: 09 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? of SERDES Framer Interface Level 5? Optical Internetworking Forum? Virtex-6?

This application note by Xilinx discusses the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum. The interface must operate bidirectionally at a payload data rate of 40 Gb/s with 0C25% forward error correction (FEC) overhead, up to a maximum of 50 Gb/s. The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew differences between the transmission paths of the data channels.

SFI-5 is intended to interface between a SERDES component and an FEC processor, between an FEC processor and a framer, or directly between a SERDES component and an FEC processor. The reference model consists of 16 data channels and a 17th channel called the deskew channel (TXDSC/RXDSC), which transmits out-of-band data samples to enable an algorithm in the receiver to deskew the 16 data channels.

View the PDF document for more information.

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