Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

Perform asynchronous oversampling in FPGA

Posted: 10 Dec 2010 ?? ?Print Version ?Bookmark and Share

Keywords:Virtex-6? SelectIO? mixed-mode clock manager?

The Virtex-6 FPGA SelectIO technology can perform 4X asynchronous oversampling at 1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the mixed-mode clock manager (MMCM) dedicated performance path. The ISERDESE1 is located in the SelectIO logic block and contains four phases of dedicated flip-flops used for sampling. The MMCM is an advanced PLL that has the capability to provide a phase-shifted clock on a low-jitter performance path.

The output of the ISERDESE1 is then sorted using a data recovery unit (DRU). The DRU used in this application note is based on a voter system that compares the outputs and selects the best data sample.

View the PDF document for more information.





Article Comments - Perform asynchronous oversampling in...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top